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Survey on memory and devices disaggregation solutions for HPC systems
- Maciej Bielski #1, Christian Pinto, Daniel Raho, Renaud Pacalet #1
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- References
- 19th IEEE International Conference on Computational Science and Engineering - CSE 2016, Paris, France, August 2016,
- Abstract
Traditionally, HPC workloads are characterized by different requirements in CPU and memory resources, which in addition vary over time in unpredictable manner. For this reason, HPC system designs, assuming physical co-location of CPU and memory on a single motherboard, strongly limit scalability, while leading to inefficient resources over-provisioning. Also, peripherals available in the system need to be globally accessible to allow optimal usage. In this context, modern HPC designs tend to support disaggregated memory, compute nodes, remote peripherals and hardware extensions to support virtualization techniques. In this paper, a qualitative survey on different attempts of memory and devices disaggregation is conducted. In addition, alternative future directions for devices disaggregation are proposed in the context of the work planned in the H2020 dRedBox project.
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- Paper in proceedings
- Research Area(s)
- Computer Science
Computer Science/Emerging Technologies
Computer Science/Hardware Architecture
Engineering Sciences/Electronics
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Bibliographic key MB:CSE-2016
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- Last update
- on february 20, 2017 by Renaud Pacalet
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