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Test Sequence Generation From Formally Verified SysML Models
- Pierre De Saqui-Sannes, Ludovic Apvrille
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- References
- 1st Workshop on Avionics Systems and Software Engineering (AvioSE'2019), Stuttgartn Germany, February 2019,
- Abstract
Test generation has been acknowledged as a cost-prone activity reducing productivity and time to market. The expected benefits of Model Based Systems Engineering include automated generation of test sequences from models. The paper proposes verification solutions for the System Modeling Lan- guage (SysML). In particular, the paper shows how to link test generation to formal verification. The proposed algorithms are implemented by the free software TTool. Two case studies support discussion on conformance and interoperability testing, respectively.
- Keywords
- Category
- Paper in proceedings
- Research Area(s)
- Computer Science/Computation and Language
Computer Science/Software Engineering
Computer Science/Computer Aided Engineering
Computer Science/Programming Languages
Computer Science/Logic in Computer Science
Computer Science/Modeling and Simulation
Computer Science/Networking and Internet Architecture
- Identifier(s)
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Bibliographic key PDSS-AVIO-19
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- Last update
- on february 21, 2019 by Ludovic Apvrille
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